modelsim的錯誤顯示

vsim work.testbench

# vsim work.testbench# Loading rtl_work.testbench

# ** Error: (vsim-3033) D:/my_eda/iwcc/testbench.v(12): Instantiation of 'iwcc' failed. The design unit was not found.

#         Region: /testbench

#         Searched libraries:

#             rtl_work

# Error loading design

# Error: Error loading design

#        Pausing macro execution

# MACRO ./iwcc_run_msim_rtl_verilog.do PAUSED at line 40

testbench下載不了，下面是testbench的程序

`timescale 1ns/1psmodule testbench();  

 reg din;  

 reg vzcs;  

 reg clkpll;  

 reg reset;  

 wire [8:1] vpeak; 

  wire dm; 

  iwcc maaaa   (   .clk_pll(clkpll),.reset(reset),.din(din),   .vzcs(vzcs),.dm(dm),.vpeak(vpeak)   ); 

  initial   

  begin     

 din=1'd1;   

   //vzcs=1'd0;  

    clkpll=1'b0;  

    reset=1'b0;  

    #80 reset=1'b1;   

  end  

 always #25 clkpll=!clkpll;  

 initial 

  fork

#0 vzcs = 1'd0;#14050 din = 1'd1;

#88950 din = 1'd0;#89150 vzcs = 1'd1;

#94300 vzcs = 1'd0;#98050 din = 1'd1;

#110450 din = 1'd0;#110600 vzcs = 1'd1;

#112050 din = 1'd1;

join

endmodule